Methods for forming silicon-containing epitaxial layers and related semiconductor device structures

ABSTRACT

A method for forming a silicon-containing epitaxial layer is disclosed. The method may include, heating a substrate to a temperature of less than approximately 950° C. and exposing the substrate to a first silicon source comprising a hydrogenated silicon source, a second silicon source, a dopant source, and a halogen source. The method may also include depositing a silicon-containing epitaxial layer wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×10 21  atoms per cubic centimeter.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

The present disclosure claims the benefit of U.S. Provisional Patent Application No. 62/503,192, filed on May 8, 2017 and entitled “METHODS FOR FORMING SILICON-CONTAINING EPITAXIAL LAYERS AND RELATED SEMICONDUCTOR DEVICE STRUCTURES,” which is incorporated herein by reference.

FIELD OF INVENTION

The present disclosure generally relates to methods for forming silicon-containing epitaxial layers and related semiconductor device structures including silicon-containing epitaxial layers. The present disclosure also generally relates to methods of forming a doped silicon epitaxial layer by chemical vapor deposition and related semiconductor device structures including doped silicon epitaxial layers.

BACKGROUND OF THE DISCLOSURE

In the field of chemical vapor deposition (CVD) of silicon-containing epitaxial layers, the trend is towards a reduction in the deposition temperature of the CVD process primarily due to the decreasing thermal budget required for the fabrication of state of the art semiconductor device structures, such as, for example, complementary metal-oxide-semiconductor (CMOS) device structures.

The reduction in the growth temperature for CVD processes may limit the growth rate of silicon-containing epitaxial layers and hence the throughput of semiconductor device wafers through the semiconductor deposition equipment. In addition, the reduction in the growth temperature of CVD processes may also limit the concentration of dopant species incorporated in the silicon-containing epitaxial layers, which may in turn have a detrimental effect on the semiconductor device performance.

Cyclic deposition and etching processes (CDE) may be utilized for low temperature deposition with favorable growth rates and selectivity. However, CVD processes which do not utilize a CDE process may be desirable which are capable of depositing silicon-containing epitaxial layers at reduced deposition temperatures with an increased incorporation of specific dopants.

SUMMARY OF THE DISCLOSURE

In accordance with at least one embodiment of the disclosure, a method for forming a silicon-containing epitaxial layer is disclosed. The method may comprise: heating a substrate to a temperature of less than approximately 950° C., exposing the substrate to a first silicon source comprising a hydrogenated silicon precursor, a second silicon source, a dopant source, and a halogen source. The method may also comprise depositing a silicon-containing epitaxial layer, wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×10²¹ atoms per cubic centimeter.

In accordance with another embodiment of the disclosure, a method for forming a doped silicon epitaxial layer by chemical vapor deposition may be provided. The method may comprise: heating a substrate disposed within a reaction chamber to a temperature of less than approximately 950° C. and exposing the substrate to a gas mixture, wherein the gas mixture comprises a first silicon source comprising silane, a second silicon source comprising a chlorinated silicon precursor, a halogen source, and a dopant source. The method may also comprise depositing a doped silicon layer on the substrate, wherein the dopant concentration within the doped silicon epitaxial layer is greater than 3×10²¹ atoms per cubic centimeter.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

While the specification concludes with claims particularly pointing out and distinctly claiming what are regarded as embodiments of the invention, the advantages of embodiments of the disclosure may be more readily ascertained from the description of certain examples of the embodiments of the disclosure when read in conjunction with the accompanying drawing, in which:

FIG. 1 illustrates a process flow diagram illustrating an exemplary deposition method in accordance with embodiments of the disclosure; and

FIG. 2 illustrates a semiconductor device structure including a silicon-containing layer formed by the embodiments of the disclosure.

It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of illustrated embodiments of the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Although certain embodiments and examples are disclosed below, it will be understood by those in the art that the invention extends beyond the specifically disclosed embodiments and/or uses of the invention and obvious modifications and equivalents thereof. Thus, it is intended that the scope of the invention disclosed should not be limited by the particular disclosed embodiments described below.

As used herein, the term “substrate” may refer to any underlying material or materials that may be used, or upon which, a device, a circuit or a film may be formed.

As used herein, the term “epitaxial layer” may refer to a substantially single crystalline layer upon an underlying substantially single crystalline substrate.

As used herein, the term “hydrogenated silicon source” may refer to a source of silicon having hydrogen incorporated therein.

As used herein, the term “chlorinated silicon source” may refer to a source of silicon having chlorine incorporated therein.

As used herein, the term “chemical vapor deposition” may refer to any process wherein a substrate is exposed to one or more volatile precursors, which react and/or decompose on a substrate surface to produce a desired deposition.

The embodiments of the disclosure may include methods for forming silicon-containing epitaxial layers and particularly for forming silicon-containing epitaxial layers at reduced deposition temperatures with increased dopant incorporation. As a non-limiting example, the methods of the disclosure may enable the deposition of silicon-containing epitaxial layers which contain a dopant concentration of greater than 3×10²¹ atoms per cubic centimeter. The silicon-containing epitaxial layer of the current disclosure may be strained by the high dopant incorporation which may in turn improve the charge transport properties of the deposited epitaxial layer, for example, by increasing the mobility of charge carriers in the silicon-containing epitaxial layers. In some embodiments of the current disclosure the silicon-containing epitaxial layer may be fully strained, i.e., the layer is free of strain relaxation and therefore may be substantially free of dislocations formed as a result of strain relaxation processes.

The methods of the disclosure may be understood with reference to FIG. 1 which illustrates a non-limiting example embodiment of a method for forming a silicon-containing epitaxial layer. For example, FIG. 1 may illustrate a method 100 for forming a silicon-containing epitaxial layer which may comprise a process block 110 wherein a substrate may be provide into a reaction chamber. As a non-limiting example, the reaction chamber may comprise a reaction chamber of a chemical vapor deposition system. However, it is also contemplated that other reaction chambers and alternative chemical vapor deposition system from other manufacturers may also be utilized to perform the embodiments of the present disclosure.

In some embodiments of the disclosure the substrate may comprise a planar substrate or a patterned substrate. Patterned substrates may comprise substrates that may include semiconductor device structures formed into or onto a surface of the substrate, for example, the patterned substrates may comprise partially fabricated semiconductor device structures such as transistors and memory elements. The substrate may contain monocrystalline surfaces and/or one or more secondary surfaces that may comprise a non-monocrystalline surface, such as a polycrystalline surface and an amorphous surface. Monocrystalline surfaces may comprise, for example, one or more of silicon (Si), silicon germanium (SiGe), silicon germanium tin (SiGeSn), or silicon carbide (SiC). Polycrystalline or amorphous surfaces may include dielectric materials, such as oxides, oxynitrides or nitrides, such as, for example, silicon oxides and silicon nitrides.

With continued reference to FIG. 1, the method 100 may continue by heating the substrate to a desired process temperature within a reaction chamber, as illustrated by a process block 120. In some embodiments of the disclosure, the method 100 may comprise heating the substrate to a temperature of less than approximately 950° C., or to a temperature of less than approximately 900° C., or to a temperature of less than approximately 850° C., or to a temperature of less than approximately 800° C., or to a temperature of less than approximately 750° C., or to a temperature of less than approximately 700° C., or to a temperature of less than approximately 650° C., or even to a temperature of less than approximately 600° C.

Once the substrate is heated to the desired process temperature the method 100 may continue by exposing the substrate to a gas mixture, as illustrated by a process block 130 of FIG. 1. In some embodiments of the disclosure exposing the substrate to a gas mixture may comprise exposing the substrate to a first silicon source comprising a hydrogenated silicon precursor, a second silicon source, a dopant source, and a halogen source.

In some embodiments of the disclosure the gas mixture may comprise a hydrogenated silicon precursor, for example, a silicon vapor precursor which includes hydrogen. For example, the method 100 may comprise selecting the hydrogenated silicon source to comprise at least one of: silane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), or tetrasilane (Si₄H₁₀). In addition the hydrogenated silicon source may comprise higher silanes with the general empirical formula Si_(x)H_((2x+2)). In some embodiments, the flow rate of the hydrogenated silicon precursor, for example, silane (SiH₄), into the reaction chamber may be less than approximately 50 sccm, or less than approximately 30 sccm, or even less than 10 sccm. In alternative embodiments of the disclosure the hydrogenated silicon precursor may be replaced by a chlorinated silicon source, examples of which are described herein.

In some embodiments of the disclosure the gas mixture may also comprise a second silicon source and in further embodiments the second silicon source may comprise a chlorinated silicon precursor, i.e., a silicon precursor or silicon reactant that includes a chlorine species. For example, in some embodiment of the disclosure the method 100 may comprise selecting the chlorinated silicon precursor to comprise at least one of monochlorosilane (MCS), dichlorosilane (DCS), trichlorosilane (TCS), hexachlorodisilane (HCDS), octachlorotrisilane (OCTS), or silicon tetrachloride (STC). In some embodiments, the flow rate of the chlorinated silicon precursor, for example dichlorosilane (DCS), into the reaction chamber may be less than approximately 1000 sccm, or less than approximately 900 sccm, or less than approximately 800 sccm, or less than approximately 700 sccm, or less than approximately 600 sccm, or less than approximately 500 sccm, or even less than approximately 400 sccm. In alternative embodiments of the disclosure the chlorinated silicon precursor may be replaced by a hydrogenated silicon source, examples of which are described herein.

In some embodiments of the disclosure the gas mixture may further comprise a dopant source, such that the deposited silicon-containing epitaxial film may be deposited with a desired conductivity characteristic and/or alloy composition. For example, in some embodiments of the disclosure the method 100 may comprise selecting the dopant source to comprise at least one of: phosphorous, boron, arsenic, gallium, aluminum, tin, or germanium. An example of a dopant source, i.e., a dopant precursor, may comprise at least one of: phosphine (PH₃), germane (GeH₄), digermane (Ge₂H₆), diborane (B₂H₆), methane (CH₄), tin chloride (SnCl₄), arsine (AsH₃), or mono-methylsilane (MMS). In some embodiments, the flow rate of the dopant source, for example phosphine (PH₃), into the reaction chamber may be less than approximately 3000 sccm, or less than approximately 1500 sccm, or less than approximately 800 sccm, or even less than approximately 400 sccm.

In some embodiments the dopant may comprise arsine (AsH₃) and in such embodiments the arsine dopant may be more effective at reducing the electrical resistivity of materials comprising tin (Sn), i.e., in materials, such as, for example, germanium tin (GeSn) and silicon germanium tin (SiGeSn). In addition, the utilization of arsine (AsH₃) as a dopant species may assist in the tin (Sn) incorporation into the deposited material and may also assist in reducing defects in the deposited layer. In some embodiments of the disclosure, the relative incorporation rate of the arsenic from the arsine (AsH₃) dopant gas may be approximately ten times greater than that of phosphorus, when utilizing phosphine (PH₃) gas as the dopant source. In addition, the incorporation of arsenic into the deposited material utilizing arsine (AsH₃) as the dopant gas may be more electrically active than the incorporation of phosphorus in to the deposited material when utilizing phosphine (PH₃).

In some embodiments of the disclosure the gas mixture may further comprise a halogen source. For example, in some embodiments of the disclosure, the method 100 may comprise selecting the halogen source, e.g., the halogen precursor, to comprise at least one of: hydrogen chloride (HCl) or chlorine (Cl₂). In some embodiments, the flow rate of the halogen source, for example, hydrogen chloride (HCl), into the reaction chamber may be less than approximately 150 sccm, or less than approximately 100 sccm, or even less than approximately 50 sccm.

In some embodiment of the disclosure the gas mixture may further comprise one or more carrier gases utilized in the transport of the precursor reactants to the heated substrate for deposition of a silicon-containing epitaxial layer, for example, hydrogen (H₂) and/or nitrogen (N₂) gases may be utilized as carrier gases.

Method 100 of FIG. 1 may proceed with a process block 140 wherein the method further comprises, forming a silicon-containing epitaxial layer on the substrate, for example, by depositing a silicon-containing epitaxial layer. In some non-limiting example embodiments of the disclosure, the silicon-containing epitaxial layer may comprise at least one of: silicon (Si), silicon germanium (SiGe), silicon germanium tin (SiGeSn), or silicon carbide (SiC). In further embodiments of the disclosure, the silicon-containing epitaxial layer may comprise one or more dopants, forming materials such as, but not limited to, phosphorus doped silicon (Si:P), boron doped silicon (Si:B), arsenic doped silicon (Si:As), gallium doped silicon (Si:Ga) phosphorous doped silicon germanium (SiGe:P), boron doped silicon germanium (SiGe:B), arsenic doped silicon germanium (SiGe:As), gallium doped silicon germanium (SiGe:Ga), phosphorous doped silicon germanium tin (SiGeSn:P), boron doped silicon germanium tin (SiGeSn:B), arsenic doped silicon germanium tin (SiGeSn:As), or gallium doped silicon germanium tin (SiGeSn:Ga).

The example embodiments of the disclosure presented herein may allow for the formation of silicon—containing epitaxial layers with high dopant concentrations at reduced deposition temperatures. For example, in some embodiments of the disclosure, forming the silicon-containing epitaxial layer may comprise forming the silicon-containing epitaxial layer wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×10²¹ atoms per cubic centimeter, or wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 1×10²¹ atoms per cubic centimeter, or even wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 1×10²⁰ atoms per cubic centimeter. As a non-limiting example embodiment of the present disclosure, the method 100 may be capable of forming a silicon epitaxial layer with a phosphorous dopant concentration of greater than 3×10²¹ atoms per cubic centimeter.

In addition to providing methods for forming a silicon-containing epitaxial layer with a high dopant concentration at low deposition temperatures, the methods of the disclosure may provide silicon-containing epitaxial layers, which are fully strained. In other words, the method of the disclosure may comprise forming a silicon-containing epitaxial layer wherein depositing the silicon-containing epitaxial layer further comprises depositing a fully strained silicon-containing epitaxial layer. In such methods, the silicon-containing epitaxial layer is fully strained to the underlying crystalline substrate or material and is therefore at least substantially free of dislocations, which form due to strain relaxation processes in the crystalline structure.

The method 100 may comprise forming a silicon-containing epitaxial layer on a substrate to a thickness of greater than 15 approximately nanometers, or to a thickness of greater than approximately 30 nanometers, or to a thickness of greater than approximately 50 nanometers, or even to a thickness of greater than approximately 100 nanometers. For example, methods of the disclosure may provide methods for depositing a silicon-containing epitaxial layer to thickness of greater than 50 nanometers wherein the silicon-containing epitaxial layer is fully strained and is at least substantially free of strain relaxation. In other embodiments of the disclosure, methods of the disclosure may provide methods for depositing a silicon-containing epitaxial layer to a thickness of greater than 75 nanometers wherein the silicon-containing epitaxial is fully strained and is at least substantially free of strain relaxation. In yet further embodiments of the disclosure, methods of the disclosure may provide methods for depositing a silicon-containing epitaxial layer to a thickness of greater than 100 nanometers wherein the silicon-containing epitaxial layer is fully strained and is at least substantially free of strain relaxation.

The method 100 may also comprise forming a silicon-containing epitaxial layer on a substrate with improved thickness uniformity. For example, in some embodiments of the disclosure methods may comprise forming a silicon-containing epitaxial layer wherein the silicon-containing epitaxial layer has a thickness non-uniformity of less than 3% 1-sigma. For example, the surface roughness of a silicon-containing epitaxial film formed by the embodiments of the disclosure may be measured by atomic force microscopy (AFM) over a measurement area of 100 microns×100 microns.

In addition to the benefits previously described, the embodiments of the disclosure may also provide methods for forming, i.e., depositing, a silicon-containing epitaxial layer at greater deposition rates than previously obtained whilst still maintaining a high dopant concentration within the epitaxial layer. For example, the method 100 may provide methods for depositing the silicon-containing epitaxial layer at a growth rate of greater than approximately 50 Å/min, or at a growth rate of greater than 75 Å/min, or at a growth rate of greater than 100 Å/min, or even at a growth rate of greater than 125 Å/min. In some embodiments of the disclosure, the growth rate of the silicon-containing epitaxial layer may depend on the selection of the deposition process parameters to either provide a selective growth process or a non-selective growth process. In embodiments wherein the process parameters are selected to provide a selective growth process, the growth rate of the silicon-containing epitaxial layer may be greater than approximately 50 Å/min, whereas when the process parameters are selected to provide a non-selective growth process the growth rate of the silicon-containing epitaxial layer may be greater than approximately 130 Å/min. In some embodiments of the disclosure, the process parameters for providing a selective growth process or a non-selective growth process may depend on the composition of the gas mixture utilized in the deposition of the silicon-containing epitaxial layer. For example, a selective growth process may utilize a gas mixture during a deposition process which comprises a halogen component whereas a non-selective growth process may utilized a gas mixture during a deposition process which comprises little or substantially no halogen component. As described herein, a selective growth (or deposition) process may comprise a growth process in which a substrate comprises two or more different surfaces and the selective growth process may be selective to one surface over another surface. For example, in some embodiments the selective growth processes described herein may be selective to deposition on a silicon oxide surface, a silicon nitride surface, or a silicon surface.

As a non-limiting example embodiment of the current disclosure, methods may provide a silicon-containing epitaxial layer with a dopant concentration of greater than 3×10²¹ atoms per cubic centimeter at a deposition rate of greater than approximately 100 Å/min.

The embodiments of the disclosure may also provide semiconductor device structures comprising a silicon-containing epitaxial layer formed by the methods described herein. For example, FIG. 2 illustrates a non-limiting example of a semiconductor device structure 200, wherein semiconductor device structure comprises a partially fabricated double gate MOSFET, commonly referred to as a FinFET. The semiconductor device structure 200 may comprise a substrate 202, an initial Fin structure 204 and a secondary Fin layer 206 formed by the embodiments of the current disclosure. In some embodiments of the disclosure, the secondary Fin layer 206 may comprise a silicon epitaxial layer with a dopant concentration of greater than 3×10²¹ atoms per cubic centimeter. In some embodiments of the disclosure, the secondary Fin layer 206 may be deposited utilizing a selective deposition process.

The example embodiments of the disclosure described above do not limit the scope of the invention, since these embodiments are merely examples of the embodiments of the invention, which is defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of this invention. Indeed, various modifications of the disclosure, in addition to those shown and described herein, such as alternative useful combination of the elements described, may become apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims. 

What is claimed is:
 1. A method for forming a silicon-containing epitaxial layer, the method comprising: heating a substrate to a temperature of less than approximately 950° C.; exposing the substrate to a first silicon source comprising a hydrogenated silicon source, a second silicon source, a dopant source, and a halogen source; and depositing a silicon-containing epitaxial layer; wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×10²¹ atoms per cubic centimeter.
 2. The method of claim 1, further comprising selecting the hydrogenated silicon source to comprise at least one of silane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈) or tetrasilane (Si₄H₁₀).
 3. The method of claim 1, further comprising selecting the second silicon source to comprise a chlorinated silicon source.
 4. The method of claim 3, further comprising selecting the chlorinated silicon source to comprise at least one of: monochlorosilane (MCS), dichlorosilane (DCS), trichlorosilane (TSC), hexachlorodisilane (HODS), octachlorotrisilane (OCTS), or silicon tetrachloride (STC).
 5. The method of claim 1, further comprising selecting the dopant source to comprise at least one of: phosphorous, boron, arsenic, gallium, aluminum, tin, or germanium.
 6. The method of claim 1, further comprising selecting the halogen source to comprise at least one of: hydrogen chloride (HCl), or chlorine (Cl₂).
 7. The method of claim 1, wherein the silicon-containing epitaxial layer has a thickness non-uniformity of less than 3% 1-sigma.
 8. The method of claim 1, further comprising depositing the silicon-containing epitaxial layer at a growth rate of greater than approximately 50 Å/min.
 9. The method of claim 8, further comprising depositing the silicon-containing epitaxial layer at a growth rate of greater than approximately 125 Å/min.
 10. The method of claim 1, wherein depositing the silicon-containing epitaxial layer further comprises depositing a fully strained silicon-containing epitaxial layer.
 11. The method of claim 1, wherein the silicon-containing epitaxial layer comprises at least one of: Si, Si:P, Si:B, Si:B:C, SiGe, SiGe:C. SiGe:P, SiGe:B, SiGeSn:P, or SiGeSn:B.
 12. The method of claim 1, further comprising depositing the silicon-containing epitaxial layer to a thickness of greater than 100 nanometers.
 13. A semiconductor device structure comprising the silicon-containing epitaxial layer formed by the method of claim
 1. 14. A method of forming a doped silicon epitaxial layer by chemical vapor deposition, the method comprising: heating a substrate disposed within a reaction chamber to a temperature of less than approximately 950° C.; exposing the substrate to a gas mixture, wherein the gas mixture comprises: a first silicon source comprising silane; a second silicon source comprising a chlorinated silicon source; a halogen source; and a dopant source; and depositing a doped silicon epitaxial layer on the substrate; wherein the dopant concentration within the doped silicon epitaxial layer is greater than 3×10²¹ atoms per cubic centimeter.
 15. The method of claim 14, further comprising selecting the chlorinated silicon source to comprise at least one of: monochlorosilane (MCS), dichlorosilane (DCS), trichlorosilane (TSC), hexachlorodisilane (HODS), octachlorotrisilane (OCTS) or silicon tetrachloride (STC).
 16. The method of claim 14, further comprising selecting the dopant source to comprise at least one of: phosphorous, boron, arsenic, gallium, aluminum, tin or germanium.
 17. The method of claim 14, further comprising selecting the halogen source to comprise at least one of: hydrogen chloride (HCl) or chlorine (Cl₂).
 18. The method of claim 14, further comprising depositing the doped silicon epitaxial layer at a growth rate of greater than approximately 100 Å/min.
 19. The method of claim 14, wherein depositing the doped silicon epitaxial layer further comprises depositing a fully strained doped silicon epitaxial layer.
 20. A semiconductor device structure comprising the doped silicon epitaxial layer formed by the method of claim
 14. 